Integrated circuits are produced as dies on a semiconductor wafer. The semiconductor wafer is subjected to various processing steps, including: forming active areas within the semiconductor material by use of doping and ion implantation; deposition and patterning of insulator layers; and forming conductors such as metallic layers. The insulator layers are formed over the semiconductor substrate, and are also formed between and surrounding conductive layers such as doped polysilicon, aluminum, and copper conductors, and over the entire structure to provide electrical insulation between layers of conductors. Another insulator layer is formed over the entire device and is referred to as the “passivation layer.” The passivation layer provides electrical insulation as well as protection from moisture and other impurities that can corrode or adversely affect the conductors and semiconductor substrate. The insulator layers are thin, brittle layers of materials that can be sometimes be considered ceramic materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, and polyimide, to name but a few.
After the integrated circuits are completely manufactured but while the integrated circuits still reside on a single semiconductor wafer, the devices are separated one from another. This operation is referred to as “singulation” or “dicing” of the semiconductor wafer. Singulation of integrated circuit devices from a semiconductor wafer includes physically separating the devices by a sawing or scribing operation. Mechanical sawing or laser sawing is used to saw through the semiconductor wafer in kerf lanes or scribe street areas that are defined between the integrated circuit dies. Laser scribing followed by a mechanical break along a scribed area is also sometimes used.
When the semiconductor wafer is sawed, cracks can form in the insulation layers at the kerf lane edge. Chips and cracks along the kerf lane are often visible after dicing. These cracks are formed because the mechanical sawing operation is relatively violent. During dicing or singulation, a rotating saw blade has to cut through the insulating layers, the conductor layers, and through the semiconductor wafer. The saw has significant vibration and heat is generated while the blade is rotating and cutting through these mechanically brittle layers. Cracks in a brittle insulator layer can propagate within that layer from the kerf lane into the surrounding areas. The cracks can propagate in the brittle insulator layers from the scribe street and into the integrated circuit dies and damage them. These cracks can destroy otherwise good integrated circuit devices. Even if a crack in an insulator layer does not propagate into the integrated circuit, cracks in the insulator layers can allow moisture incursion from the edge of the integrated circuit at the scribe line into the device. Moisture incursion contributes to corrosion of structures inside the integrated circuit and can lead to additional failures. Unwanted moisture can also increase the delamination of certain thin films deposited over the substrate within the integrated circuit. Other impurities can also enter the integrated circuit due to the cracks initiated in the sawing operation, even when the integrated circuit is still otherwise functional.
In alternative wafer dicing operations, laser cutting can be used. In one approach a laser is used to scribe trenches into the surface of the wafer, and the wafer is then broken mechanically along the cuts. In other approaches the laser is used to cut through the semiconductor wafer. In either of these laser dicing approaches, cracks in the insulating layers can also occur that can propagate from the kerf line and into the integrated circuit dies.
U.S. Pat. No. 6,521,975, entitled “Scribe Street Seals in Semiconductor Devices and Method of Fabrication,” filed May 15, 2000, issued Feb. 18, 2003, listing West et. al. as inventors, which is co-owned with the present application, and which is hereby incorporated by reference in its entirety herein, describes forming scribe seals including conductors and conductive vias extending through the layers of insulators between conductors to prevent cracks from propagating from a dicing line where a semiconductor wafer is cut.
U.S. Pat. No. 8,125,053, entitled “Embedded Scribe Lane Crack Arrest Structure for Improved IC Package Reliability of Plastic Flip-Chip Devices,” filed Feb. 4, 2004, issued Feb. 28, 2012, listing West et. al. as inventors, which is co-owned with the present application, and which is hereby incorporated by reference in its entirety herein, discloses adding crack arrest structures between the scribe streets and the scribe seals to further prevent crack propagation from the scribe line area.